1. Field of the Invention
The present invention relates to a process for fabricating MOS semiconductor devices, and more particularly for fabricating power MOS transistors with a vertical current flow, and to the resulting structures.
2. Description of the Prior Art
It is known in the art to form n-channel and p-channel power MOSFET devices. These devices are typically doubly-diffused MOS devices with a vertical current flow (VDMOS), and may be fabricated as discrete devices or incorporated into integrated circuits having other devices, such as a control circuit combined with a power stage.
In general, one known technique for forming such power devices includes growing a lightly doped epitaxial layer of a first conductivity type on a heavily doped silicon substrate which is also doped with the first conductivity type. Standard field oxidation and masking steps are performed, followed by implantation and diffusion of a highly doped region of a second conductivity type in the epitaxial layer. Active areas are then defined on the device using a masking step, followed by the formation of gate oxide and polycrystalline silicon layers. The polycrystalline and gate oxide layers are then masked and etched to define a gate. A lightly doped region of the second conductivity type is then formed at the sides of, and underneath, the gate for the formation of a channel region. Highly doped regions of the first conductivity type are formed adjacent to the gate to provide source regions. Later steps include the deposition of oxide over the polycrystalline silicon, definition of contact areas and metallization of the entire surface over the device, and passivation of the device. Metallization is provided for the backside of the substrate to create a drain.
Formation of power MOS devices in such a manner results in the formation of bipolar parasitic transistors on each side of the gate region. In the case of an n-channel power transistor, the parasitic bipolar transistor is an NPN transistor. The emitter of the parasitic bipolar transistor is formed by the source region, the body region forms the base, and the epitaxial layer is the collector of the parasitic device.
The metallization formed over the surface of the MOS transistor causes the base and emitter of the parasitic transistor to be substantially short circuited. The short circuit is somewhat limited by the internal resistances of the device between the surface of the power transistor and the body region under the source. This resistance constitutes the base extrinsic resistance of the parasitic transistor.
These resistances are lower in the highly doped body regions, where the high doping levels cause an increase in carrier recombinations and diminish the possibility of current flowing from the emitter to the collector. The gain of the parasitic transistor is also low in such highly doped regions. The base resistance, and transistor gain, have higher values in the body regions having lower dopant concentrations.
The importance of having low gain and low resistances for the parasitic transistors may be observed by realizing that whenever the rate of variation of the voltage applied across the MOS transistor is sufficiently high, capacitance current flowing through the extrinsic base resistance of the parasitic transistor base can bias it on and cause it to switch into operation in the active region. This causes the power transistor to have a breakdown voltage equal to that of the parasitic transistor with its base not short circuited to the emitter, which is obviously lower than otherwise typical of the power MOS transistor.
Therefore, the presence of the parasitic bipolar transistors has the effect of lowering the breakdown voltage of the power MOS transistor, and of reducing the switching speed of such device. A lower gain and base extrinsic resistance for the parasitic bipolar transistors results in a higher voltage rate of change required to turn on the parasitic bipolar device. This result in an improved VDMOS device.
Known prior art power devices have a number of important drawbacks. Two distinct masking steps are typically used to define a channel region and a highly doped body region. One result of using two masks is a possibility of misalignment between the highly doped body region and the polycrystalline silicon gate structure. It is possible for the highly doped body region to penetrate into the channel region, where the increase of dopant causes a rise the conduction threshold voltage of the transistor. Also, the source-drain resistance of the device increases during transistor conduction.
A further drawback of the prior art results from the greater junction depth of the highly doped body region with respect to a lower doped body region. During device conduction, the source-drain resistance rises as the epitaxial layer thickness increases. The breakdown voltage is controlled by the minimum thickness of the epitaxial layer under the body region, and is therefore lower for an increase in junction thickness in the highly doped body region. Such a disparity in results does not allow for optimization of the source-drain resistance for a given breakdown voltage.